| 摘要 | 第6-7页 |
| Abstract | 第7页 |
| Acknowledgements | 第8-9页 |
| Table of Contents | 第9-11页 |
| List of Figures | 第11-19页 |
| 1 Introduction | 第19-28页 |
| 1.1 Scaling of CMOS Devices and Modeling Issues | 第19-21页 |
| 1.2 Classification of Transport Models | 第21-22页 |
| 1.3 Overview of Non-equilibrium Green's Function(NEGF) | 第22-26页 |
| 1.4 Outline of the Thesis | 第26-28页 |
| 2 Analytical Models of Advanced MOSFETs in Quasi Ballistic Regime | 第28-54页 |
| 2.1 Introduction | 第28-30页 |
| 2.2 The Natori-Lundstrom Models of Quasi Ballistic Transport | 第30-38页 |
| 2.2.1 The Natori's Model of Ballistic Transport | 第30-31页 |
| 2.2.2 Injection Velocity and Subband Engineering | 第31-35页 |
| 2.2.3 Lundstrom's Model of Backscattering | 第35-38页 |
| 2.3 Beyond the Natori-Lundstrom Model | 第38-45页 |
| 2.3.1 Theoretical Foundations of Natori-Lundstrom Model:The Quasi Ballistic Drift-Diffusion Theory | 第38-40页 |
| 2.3.2 Comparison with Monte Carlo Simulations:Results and Discussion | 第40-45页 |
| 2.4 Electrical Characterization of MOSFETs in Quasi Ballistic Regime | 第45-53页 |
| 2.4.1 Introduction and State of the Art | 第45-46页 |
| 2.4.2 Principle of Backscatte ring Coefficient Extraction in the Linear Regime | 第46-47页 |
| 2.4.3 Results and Discussion | 第47-53页 |
| 2.5 Conclusion | 第53-54页 |
| 3 A Top of The Barrier Model for Ballistic MOSFETs | 第54-68页 |
| 3.1 Introduction | 第54-55页 |
| 3.2 Device Physics of Ballistic MOSFETs | 第55-59页 |
| 3.3 Development of Transport Model for Ballistic MOSFETs | 第59-62页 |
| 3.4 Applications to Ballistic MOSFETs | 第62-67页 |
| 3.4.1 Parameters for the Analytical Model | 第63-64页 |
| 3.4.2 Treatment of Floating Source Potential in the Analytical Model | 第64-66页 |
| 3.4.3 Velocity and Charge at the Top of the Barrier | 第66-67页 |
| 3.5 Discussion | 第67页 |
| 3.6 Summary and Conclusion | 第67-68页 |
| 4 Simulation of Ballistic Transport in Nanowire Transistors | 第68-86页 |
| 4.1 Introduction | 第68-69页 |
| 4.2 Boltazmann Transport Equation in Ballistic Limit | 第69-72页 |
| 4.3 Structure of Nanowire Transistor | 第72-74页 |
| 4.4 Simulation Results and Discussion | 第74-75页 |
| 4.5 Conclusion | 第75-86页 |
| 5 Harmonic Spectrum Analysis and Transistor Model Verification | 第86-125页 |
| 5.1 Introduction | 第86-87页 |
| 5.2 Transistor Model Quality and Input Signal | 第87-90页 |
| 5.2.1 Discontinuity due to Transistor Model | 第87-88页 |
| 5.2.2 Discontinuity due to Input Signal | 第88-90页 |
| 5.3 Simulations of an Inverter using 65nm and 130nm Process Technologies | 第90-96页 |
| S.3.1 Simulations of an Inverter using 65nm Process Technology | 第90-93页 |
| 5.3.2 Simulations of an Inverter using 130nm Process Technology | 第93-96页 |
| 5.3.3 Comparison between the Simulation Results of 130nm and 65nm Process Technologies | 第96页 |
| 5.4 Flip Flop Topologies and Simulations | 第96-122页 |
| 5.4.1 Flip Flops and Latches | 第96-98页 |
| 5.4.2 Flip-Flop and Latch Topologies Consideration in our Simulation | 第98-99页 |
| 5.4.3 PowerPC 603 Master-Slave Latch | 第99-108页 |
| 5.4.4 Modified C~2MOS Latch | 第108-115页 |
| 5.4.5 Hybrid Latch Flip-Flop(HLFF) | 第115-122页 |
| 5.5 Discussion and Comparison among Flip-Flop and Latch Topologies | 第122-124页 |
| 5.6 Couclusion | 第124-125页 |
| 6 Summary and future work | 第125-129页 |
| 6.1 Summary | 第125-126页 |
| 6.2 Future work | 第126-129页 |
| References | 第129-141页 |
| Appendix | 第141-145页 |
